apex signal, a division of nai, inc. bohemia, ny 11716 usa model pc104-73dl1 specifications pc104- 73dl1 rev d www.naii.com code: 0vgu1 sheet 1 of 4 pc104-73dl1 lvdt/rvdt output, programmable 16 bit resolution; wrap-around self test on-board programmable excitation supply (optional) features : ? 16 bit resolution ? continuous background bit testing and excitation loss detection ? transformer isolated ? no adju stments or trimming required ? part number, s/n, date code, & rev. in permanent memory description : this pc104 compliant stackthrough module offers (1) three-wire transformer isolated ?programmable? lvdt/rvdt outputs with wrap-around self test and optional excitation supply. instead of buying cards that are set for specific outputs, the uniqueness of this design makes it possible to buy our generic card that can be programmed and reprogrammed in the field for any excitation and signal voltage between 2.0 and 28 volts. one transformer isolated excitation is supplied for the a, b output pair. user selects the desired a+b voltage. after this is done, the card will automatically set the correct b voltage for any programmed a voltage. use of a ratiometric design eliminates errors caused by excitation voltage variations. the outputs are stable with temperature and switching spikes are not noticeable . to simplify logistics, part number, s/n, date code, & rev. are located in permanent memory locations. automatic background bit testing where the output of each channel is compared against the commanded input to a testing accuracy of 0.1% fs and each signal and excitation is monitored. any failure triggers a flag. the testing is totally transparent to the user, requires no external programming, has no effect on the standard operation of this card and can be enabled or disabled via the bus. the results are available in status registers. principal of operation (lvdt): typically the primary is excited by an ac source, causing a magnetic flux to be generated within the transducer. voltages are induced in the two secondaries, with the magnitude varying with the position of the core. usually, the secondaries are connected in series opposition, causing a net output voltage of zero when the core is at the electrical center. when the core is displaced in either direction from center the voltage increases linearly either in phase or out of phase with the excitation depending on the direction. interfacing lvdt to converter two common connection methods are: 1. primary as reference (two-wire system) 2. derived reference (three/four-wire lvdt) two-wire system: this method of connection converts the widest range of lvdt sensors and. is the most sensitive to excitation voltage variations, temperature and phase shift effects. three/four-wire lvdt: the lvdt is again excited from the primary side, but the converter reference is the sum of a + b that has constant amplitude for changing core displacement this system is insensitive to temperature effects, phase shifts and oscillator instability and solves the identity (a-b)/(a+b)
apex signal, a division of nai, inc. bohemia, ny 11716 usa model pc104-73dl1 specifications pc104-73dl1 rev d www.naii.com code: 0vgu1 sheet 2 of 4 va-vb=-10v va+vb=10v example uses a 10.0 vrms output 5.0 v 0.0 v 10.0 v va=0v vb=10v position va-vb=0v va+vb=10v va 0% 50% vb=5v va=5v vb va-vb=10v va+vb=10v vb=0v 100% va=10v (usual lvdt configuration) (in-phase) a 4 wire excitation b 3 wire excitation a b a-b a+b specifications : resolution: 16 bits (.001526% fs) linearity: 1 mv + .05% reading offset: 1 mv output format: 3-wire or 4-wire. transformer isolated. output voltage: 2.0 to 28 vrms 1% at no load, programmable with tr. transformer isolated. output voltage will vary directly with excitation. load: with output voltages from 2.0 to 7.0 vrms: 2.5 k w min. with output voltages from 7.1 to 20.0 vrms: 10 k w min. with output voltages from 10.1 to 28.0 vrms: 15 k w min. short circuit protected. regulation: 1% max. excitation: 2.0-28 vrms, programmable, 0.1 v resolution. transformer isolated. (250 mw) frequency: 360 hz to 10 khz, broadband. phase shift (input to output): 0.1 max. excitation z in: 50 k w min. power: +5 vdc 5% at 0.35 a 12 vdc 5% at 0.5 a temperature: -40c to +80 c storage temperature: -55c to +105c. size: 3.6 x 3.8 x 0.6 weight: 12 oz. output voltage: output a= ref*tr* (position / 65536) output b= ref*tr* 1- (position / 65536) transformation ratio (tr): [(output a + output b) / ref) * 65536
apex signal, a division of nai, inc. bohemia, ny 11716 usa model pc104-73dl1 specifications pc104-73dl1 rev d www.naii.com code: 0vgu1 sheet 3 of 4 programming instructions: i/o configuration : this card requires 32 consecutive addresses in the i/o address space on a 32 byte boundary. the base address is switch settable in the 000-3e0 hex (0 to 992) address range. address= base + offset base a9 a8 a7 a6 a5 offset a4 a3 a2 a1 a0 decimal equiv. sw5 * 32 sw4 * 64 sw3 * 128 sw2 * 256 sw1 * 512 * ?1? = off ?0? = on note: base addresses to avoid: 320-32f hard disk 3b0-3bf monochrome display 3f8-3ff asynch comm i/o 378-37f parallel printer port 3f0-3f7 floppy disk offset 00 position lo read/write 07 freq. out hi write/read 0d model number hi read 15 rev level hi read 01 position hi read/write 08 excitation. lo write/read 10 serial number lo read 16 status, signal read 02 wrap-around lo read/write 09 excitation hi write/read 11 serial number lo read 18 status, excitation read 03 wrap-around hi read/write 0a tr lo write/read 12 date code lo read 04 status, accuracy read 0b tr hi write/read 13 date code hi read 06 freq. out lo write/read 0c model number lo read 14 rev level lo read hi byte lo byte d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 data, max. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 data, 1/2 scale, max. 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data, zero 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data, 1/2 scale, min. 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 data, min. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 status, signal x x x x x x x x x x x x x x b a status, excitation x x x x x x x x x x x x x x x d status, test x x x x x x x x x x x x x x x d codes are in 2's complement. examples of voltage programming 256 128 64 32 16 8 4 2 1 28.1 vrms entered as 281 1 0 0 0 1 1 0 0 1 7.0 vrms entered as 70 0 0 1 0 0 0 1 1 0
apex signal, a division of nai, inc. bohemia, ny 11716 usa model pc104-73dl1 specifications pc104-73dl1 rev d www.naii.com code: 0vgu1 sheet 4 of 4 programming instructions : power on: sets all outputs to zero, optional excitation supply to 360 hz and no output. wrap around : can be read at any time and indicates the actual output. read the hi byte first. hi byte read holds lo byte until read. optional excitation supply: for frequency, write a 16 bit word (ex: 400 hz = 110010000) to 06h/07h. for voltage, write a 16 bit word (ex: 26.1 vrms =100000101) with lsb=0.1 vrms, to 08h/09h. it is recommended that user program the required frequency before setting the output voltage. to read status : read 18h for excitation, 16h for signal, 04h for accuracy. test: ?1? accuracy ok; ?0? failed; status: ?1? exc. on, signal on. ?0? exc. and/or signal loss. connector: samtec tsw-104-25-t-d-r-a mate: idc 4x2 .1? pin numbers pin lo hi exc. hi (in) exc. lo (in) exc. hi out) exc. lo (out) 7 5 3 1 ch.a 1 4 7 8 5 6 ch.b 3 2 8 6 4 2 facing pins part number designation environmental c = no conformal coating k = removable conformal coating l = permanent conformal coating total number channels options 0 = none 9 = custom (see separate spec) reference supply r = on-board reference 73dl1- 1 x x x x bus 1 = 8-bit isa bus 2 = 16-bit isa bus
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